1) In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
a. Netlist
b. Checklist
c. Shitlist
d. Dualist
|
Answer
Explanation
|
ANSWER: Netlist
Explanation:
No explanation is available for this question!
|
|
2) Which among the following functions are performed by MSI category of IC technology?
a. Gates, Op-amps
b. Microprocessor/A/D
c. Filters
d. Memory/DSP
|
Answer
Explanation
|
ANSWER: Filters
Explanation:
No explanation is available for this question!
|
|
3) Which among the following EDA tool is available for design simulation?
a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic
|
Answer
Explanation
|
ANSWER: VIVElogic
Explanation:
No explanation is available for this question!
|
|
4) Which among the following operation/s is/are executed in physical design or layout synthesis stage?
a. Placement of logic functions in optimized circuit in target chip
b. Interconnection of components in the chip
c. Both a and b
d. None of the above
|
Answer
Explanation
|
ANSWER: Both a and b
Explanation:
No explanation is available for this question!
|
|
5) Which among the following is/are taken into account for post-layout simulation?
a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above
|
Answer
Explanation
|
ANSWER: All of the above
Explanation:
No explanation is available for this question!
|
|
6) Which level of system implementation includes the specific function oriented registers, counters & multiplexers?
a. Module level
b. Logical level
c. Physical level
d. All of the above
|
Answer
Explanation
|
ANSWER: Module level
Explanation:
No explanation is available for this question!
|
|
7) In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
a. Floorplanning
b. Placement & Routing
c. Testing
d. Extraction
|
Answer
Explanation
|
ANSWER: Extraction
Explanation:
No explanation is available for this question!
|
|
8) _________ is the fundamental architecture block or element of a target PLD.
a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation
|
Answer
Explanation
|
ANSWER: Logic cell
Explanation:
No explanation is available for this question!
|
|
9) Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?
a. Simulation
b. Optimization
c. Synthesis
d. Verification
|
Answer
Explanation
|
ANSWER: Synthesis
Explanation:
No explanation is available for this question!
|
|
10) The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.
a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator
|
Answer
Explanation
|
ANSWER: Waveform Editor
Explanation:
No explanation is available for this question!
|
|
